Abstract:We present a design automation framework for analog circuit sizing that produces calibrated, topology-specific analytical equations from raw circuit netlists. A large language model (LLM) derives a complete Python sizing function in which each device dimension is traceable to a specific design rationale - a form of interpretable output absent from existing optimization-based and LLM-based sizing methods. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on circuits ranging from 8 to 30 transistors - spanning two-stage Miller-compensated, current-mirror, folded cascode, nested Miller-compensated, and complementary class-AB output topologies - across three process nodes (40 nm, 90 nm, 180 nm). On matched-specification benchmarks, including the class-AB opamp case, the framework converges in 2-7 simulations. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. The one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.
| Comments: | 14 pages, 4 figures, 9 tables. V2: Extended to 5 topology families (8-30 transistors), 3 process nodes, and quantitative comparison against 4 published methods |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2604.07387 [cs.AR] |
| (or arXiv:2604.07387v2 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2604.07387 arXiv-issued DOI via DataCite |
Submission history
From: Antonio Bujana [view email]
[v1]
Wed, 8 Apr 2026 04:35:25 UTC (533 KB)
[v2]
Tue, 28 Apr 2026 19:12:15 UTC (523 KB)