AI infrastructure startup XCENA has raised $135 million in a Series B round at a $570 million valuation, bringing its total funding to $185 million as investors look for ways to reduce the soaring costs of running generative AI systems, TechCrunch reported Friday.
The funding round was co-led by Altinum and IMM Investment, with participation from Corstone Asia, SBI Investment, and Mirae Asset Capital.
XCENA was founded in 2022 by CEO Jin Kim, CTO Dohun Kim, and CPO Harry Juhyun Kim, all former executives at Samsung and SK Hynix, two of the world’s largest memory chip makers.
The startup is focused on one of AI’s growing pain points: memory bottlenecks. Every AI query requires data to move repeatedly between memory, CPUs, and GPUs, forcing systems to rely on expensive, power-hungry processors throughout the inference process.
XCENA’s solution is a chip that performs compute tasks closer to DRAM, the fast memory processors actively use, reducing the need for constant transfers between hardware components.
Its flagship chip, the MX1, connects to CPUs using CXL, a high-speed interface linking processors and memory. The company says the chip processes data directly inside the memory module, allowing routine operations such as preprocessing, KV cache management, and data caching to bypass CPUs.
According to XCENA, the architecture could drastically reduce server requirements, with workloads previously needing 10 servers potentially running on one.
The company is betting that hyperscalers spending billions annually on AI infrastructure will increasingly prioritize memory efficiency as AI deployment scales. Discussions with global memory vendors are already underway.
The company plans to manufacture production chips through Samsung’s foundry operations by the end of 2026, with revenue expected to begin in 2027. The MX1 remains in prototype stage.
The startup is positioning itself against companies such as Astera Labs and Marvell in the emerging market for memory-centric AI infrastructure. XCENA says its competitive edge comes from its proprietary architecture, including thousands of small RISC-V cores and in-house designs for memory hierarchy, interconnects, and DRAM controllers.
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