Every time you ask an AI model a question, your request sets off a complex data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy computation, and then makes its way back — and that entire journey repeats for every single word the AI generates. The bottleneck is structural: it means routing through some of the most expensive and power-intensive chips in the industry on every single request.
That inefficiency is exactly what XCENA, a four-year-old startup with offices in South Korea and the U.S., is trying to solve. The company has designed a chip that places compute capabilities much closer to DRAM — the fast, short-term memory chips that store data a processor is actively using — allowing routine data operations to be handled near memory, without the costly round trips between CPUs, GPUs, and memory. If it works at scale, the implications for AI infrastructure costs could be significant.
Investors bet on a memory-first approach
Investor enthusiasm around XCENA’s thesis is clear. The startup just raised $135 million in a Series B round at a valuation of $570 million, bringing its total funding to $185 million. The round was co-led by Seoul-based venture capital firms Altinum and IMM Investment, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital.
XCENA CEO Jin Kim, who co-founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, is a veteran of Samsung and SK Hynix — the memory giants that supply chips powering Nvidia’s GPUs. “CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that,” Kim said in an interview with Bitcoin World. “The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures.”
This month, the three companies that dominate the global memory chip market — Samsung, SK Hynix, and Micron — each crossed a trillion-dollar valuation for the first time, underscoring the growing importance of memory in AI workloads.
How the MX1 chip works
XCENA is betting its business on the thesis that “inference isn’t just a compute problem; it’s increasingly a memory scaling problem,” said Kim. The company’s chip, the MX1, connects to the CPU through CXL (Compute Express Link) — essentially a dedicated express lane between the processor and memory — processing data before it ever needs to leave the memory module. It brings compute to the data, not the other way around.
The company claims that what used to require 10 servers could potentially run on just one. “While GPUs excel at matrix multiplication — the heavy math behind AI model training — much of the surrounding data orchestration, including preprocessing, KV cache management, and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself,” Kim said.
KV cache management is the system that stores prior conversation context so a model doesn’t have to reprocess it — a critical function for inference workloads that becomes increasingly memory-intensive as models scale.
Competitive landscape and timeline
Demand for memory solutions has surged since the second half of last year, and the company believes the timing is working in its favor. Conversations with several global memory vendors are in early stages, though Kim declined to name them. The company’s ideal customers are hyperscalers spending tens of billions a year on AI infrastructure, where even a small gain in memory efficiency can mean hundreds of millions in savings.
The MX1 is still a prototype. Mass production chips are scheduled to roll off Samsung’s foundry lines by the end of 2026, with the company expecting to generate revenue starting in 2027. While neural processing unit (NPU) makers are competing to challenge Nvidia for training workloads, XCENA is targeting the memory-intensive layer that sits underneath all of it.
XCENA’s closest rivals include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Marvell is a large, established player already working in the same space, Kim said, adding that the differentiator comes down to intellectual property. “We have thousands of cores,” Kim said. Based on public specs, Marvell’s approach relies on a handful of general-purpose cores by comparison. Those cores are built on RISC-V — an open-source chip design blueprint — and optimized specifically for data processing, with each core deliberately kept small and efficient. Beyond the cores themselves, XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller — a level of vertical integration that most chip companies, including larger rivals, typically outsource.
Why this matters for AI infrastructure
The core insight behind XCENA’s approach is that the cost of AI inference — the process of using a trained model to generate responses — is increasingly dominated by memory access rather than pure computation. As models grow larger and handle longer contexts, the amount of data that needs to be shuffled between memory and processors grows exponentially. By handling routine data operations directly within the memory module, XCENA’s chip could reduce both latency and power consumption, two of the biggest cost drivers in modern AI data centers.
The company, which has more than 90 staff across offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale, is also in conversations with international investors about additional funding.
Conclusion
XCENA’s $135 million raise signals strong investor confidence in a memory-centric approach to AI infrastructure. With a prototype in hand, mass production slated for late 2026, and a team of veterans from the world’s largest memory chipmakers, the startup is positioning itself to address a structural inefficiency that affects every AI workload. Whether it can deliver on its promise of reducing server requirements by a factor of ten will depend on the success of its MX1 chip in real-world deployments — but the market is clearly paying attention.
FAQs
Q1: What problem is XCENA trying to solve?
XCENA aims to eliminate the costly round trips between memory, CPUs, and GPUs that occur during every AI inference request. By placing compute capabilities directly within memory modules, the company hopes to reduce latency, power consumption, and infrastructure costs.
Q2: When will XCENA’s chip be available?
The MX1 is currently a prototype. Mass production is scheduled to begin on Samsung’s foundry lines by the end of 2026, with revenue expected to start in 2027.
Q3: Who are XCENA’s main competitors?
XCENA’s closest competitors are Astera Labs and Marvell, both of which are publicly traded companies working on next-generation memory connectivity solutions. Marvell is a larger, established player in the space, while XCENA differentiates itself with a highly parallel architecture using thousands of RISC-V cores.
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